/*
 * Jailhouse, a Linux-based partitioning hypervisor
 *
 * Configuration for demo inmate on Phytium FT2000/4
 *
 */

#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>

struct {
	struct jailhouse_cell_desc cell;
	__u64 cpus[1];
	struct jailhouse_memory mem_regions[6];
	struct jailhouse_irqchip irqchips[1];
	struct jailhouse_pci_device pci_devices[1];
	struct jailhouse_pci_capability pci_caps[7];
} __attribute__((packed)) config = {
    .cell =
        {
            .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
            .revision = JAILHOUSE_CONFIG_REVISION,
            .name = "linux",
            .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,

            .cpu_set_size = sizeof(config.cpus),
            .num_memory_regions = ARRAY_SIZE(config.mem_regions),
            .num_irqchips = ARRAY_SIZE(config.irqchips),
            .num_pci_devices = ARRAY_SIZE(config.pci_devices),
            .num_pci_caps = ARRAY_SIZE(config.pci_caps),
            .vpci_irq_base = 101,

            .console =
                {
                    .address = 0x28001000,
                    .type = JAILHOUSE_CON_TYPE_PL011,
                    .flags =
                        JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4,
                },
        },

    .cpus =
        {
            0xC,
        },

    .irqchips =
        {
            {
                .address = 0x29900000,
                .pin_base = 32,
                .pin_bitmap =
                    {
                        1 << (39 - 32),
                        0,
                        0,
                        1 << (101 + 32 - 128),
                    },
            },
        },

    .mem_regions = {
        /* UART */ {
            .phys_start = 0x28001000,
            .virt_start = 0x28001000,
            .size = 0x1000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
        },
        /* RAM */
        {
            .phys_start = 0x92000000,
            .virt_start = 0,
            .size = 0x1000000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
        },

        /* RAM */
        {
            .phys_start = 0x93000000,
            .virt_start = 0x93000000,
            .size = 0x1d000000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
                     JAILHOUSE_MEM_LOADABLE,
        },

        /* GICR_PROPBASER  GICR_PENDING {
            .phys_start = 0x2140300000,
            .virt_start = 0x2140300000,
            .size = 0x50000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
        },*/

        /* communication region */
        {
            .virt_start = 0x80000000,
            .size = 0x00001000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_COMM_REGION,
        },
        /* MemRegion: 58300000-583fffff : 0000:05:00.0 */
        {
            .phys_start = 0x58300000,
            .virt_start = 0x58000000,
            .size = 0x100000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_ROOTSHARED,
        },
        /* MemRegion: 58502000-58503fff : 0000:05:00.0 */
        {
            .phys_start = 0x58502000,
            .virt_start = 0x58102000,
            .size = 0x2000,
            .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_ROOTSHARED,
        },
#if 0
#endif
    },

    .pci_devices =
        {
            /* PCIDevice: 0000:05:00.0 */
            {
                .type = JAILHOUSE_PCI_TYPE_DEVICE,
                .domain = 0x0,
                .bdf = 0x500,
                .caps_start = 0,
                .num_caps = 7,
                .num_msi_vectors = 1,
                .msi_64bits = 1,
                .msi_maskable = 1,
                .num_msix_vectors = 5,
                .msix_region_size = 0x4000,
                .msix_address = 0x58500000,
                .bar_mask =
                    {
                        0xfff00000,
                        0x00000000,
                        0x00000000,
                        0xffff8000,
                        0x00000000,
                        0x00000000,
                    },
            },
        },
    .pci_caps =
        {
            /* PCIDevice: 0000:05:00.0 */
            {.id = PCI_CAP_ID_PM,
             .start = 0x40,
             .len = 8,
             .flags = JAILHOUSE_PCICAPS_WRITE},
            {.id = PCI_CAP_ID_MSI,
             .start = 0x50,
             .len = 32,
             .flags = JAILHOUSE_PCICAPS_WRITE},
            {.id = PCI_CAP_ID_MSIX,
             .start = 0x70,
             .len = 12,
             .flags = JAILHOUSE_PCICAPS_WRITE},
            {.id = PCI_CAP_ID_EXP,
             .start = 0xa0,
             .len = 60,
             .flags = JAILHOUSE_PCICAPS_WRITE},
            {.id = PCI_EXT_CAP_ID_ERR, .start = 0x100, .len = 64, .flags = 0},
            {.id = PCI_EXT_CAP_ID_DSN, .start = 0x140, .len = 12, .flags = 0},
            {.id = PCI_EXT_CAP_ID_TPH, .start = 0x1a0, .len = 2, .flags = 0},
        },
#if 0
#endif
};
